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semiconductor group 1 1999-03-12 5-v low-drop voltage regulator version 2.0 bipolar ic features l output voltage tolerance 2 % l low-drop voltage l very low standby current consumption l input voltage up to 40 v l overvoltage protection up to 60 v ( 400 ms) l reset function down to 1 v output voltage l esd protection up to 2000 v l adjustable reset time l on/off logic l overtemperature protection l reverse polarity protection l short-circuit proof l wide temperature range l suitable for use in automotive electronics t new type functional description tle 4267 is a 5-v low-drop voltage regulator in a to220-7 package. it supplies an output current of > 400 ma. the ic is shortcircuit-proof and incorporates temperature protection that disables the ic at overtemperature. type ordering code package tle 4267 q67000-a9153 p-to220-7-3 tle 4267 g q67006-a9169 p-to220-7-180 (smd) tle 4267 s q67000-a9246 p-to220-7-230 t tle 4267 gm q67006-a9398 p-dso-14-8 (smd) p-to220-7-3 p-to 220-7-180 (to-220 ab/7, option e3180) p-to220-7-230 p-dso-14-8 tle 4267
tle 4267 semiconductor group 2 1999-03-12 application the ic regulates an input voltage v i in the range 5.5 v < v i <40vto v qrated = 5.0 v. a reset signal is generated for an output voltage v q of < 4.5 v. the reset delay can be set with an external capacitor. the device has two logic inputs. it is turned-on by a voltage of > 4 v on e2 by the ignition for example. it remains active as a function of the voltage on e6, even if the voltage on e2 goes low. this makes it possible to implement a self-holding circuit without external components. when the device is turned-off, the output voltage drops to 0 v and current consumption tends towards 0 m a. design notes for external components the input capacitor c i is necessary for compensation line influences. the resonant circuit consisting of lead inductance and input capacitance can be damped by a resistor of approx. 1 w in series with c i . the output capacitor is necessary for the stability of the regulating circuit. stability is guaranteed at values of 3 22 m f and an esr of 3 w within the operating temperature range. circuit description the control amplifier compares a reference voltage, which is kept highly accurate by resistance adjustment, to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. saturation control as a function of the load current prevents any over-saturating of the power element. a comparator in the reset-generator block compares a reference that is independent of the input voltage to the scaled-down output voltage. if this reaches a value of 4.5 v, the reset-delay capacitor is discharged and then the reset output is set low. as the output voltage increases again, the reset-delay capacitor is charged with constant current from v q = 4.5 v onwards. when the capacitor voltage reaches the upper switching threshold, reset goes high again. the reset delay can be set within wide range by selection of the external capacitor. with the integrated turn-on/turn-off logic it is simple to implement delayed turn-off without external components.
tle 4267 semiconductor group 3 1999-03-12 truth table for turn-on/turn-off logic inhibit: e2 enable function, active high hold: e6 hold and release function, active low e2, inhibit hold v q remarks l x off initial state, inhibit internally pulled up h x on regulator switched on via inhibit, by ignition for example h l on hold clamped active to ground by controller while inhibit is still high x l on previous state remains, even ignition is shut off: self-holding state l l on ignition shut off while regulator is in self-holding state l h off regulator shut down by releasing of hold while inhibit remains low, final state. no active clamping required by external self-holding circuit ( m c) to keep regulator shut off.
tle 4267 semiconductor group 4 1999-03-12 pin configuration (top view) pin definitions and functions pin symbol function 1 i input; block to ground directly at the ic by a ceramic capacitor 2e2 inhibit; device is turned-on by high signal on this pin; internal pulldown resistor of 100 k w 3r reset output; open-collector output internally connected to the output via a resistor of 30 k w 4 gnd ground; connected to rear of chip 5d reset delay; connect with capacitor to gnd for setting delay 6e6 hold; see truth table above for function; this input is connected to output voltage across pullup resistor of 50 k w 7q 5-v output; block to gnd with 22- m f capacitor, esr < 3 w aep02123 i e2 r gnd d q 4 3 2 1567 e6 aep01481 i e2 r gnd d q 4 3 2 15 6 7 e6 p-to220-7-3 p-to220-7-230 7 6 5 1234 aep01724 e6 d gnd r e2 i p-to220-7-180
tle 4267 semiconductor group 5 1999-03-12 pin configuration (contd) (top view) pin definitions and functions pin symbol function 1 i input; block to ground directly at the ic by a ceramic capacitor 2e2 inhibit; device is turned-on by high signal on this pin; internal pulldown resistor of 100 k w 7r reset output; open-collector output internally connected to the output via a resistor of 30 k w 3, 4, 5, 10, 11, 12 gnd ground; connected to rear of chip 8d reset delay; connect with capacitor to gnd for setting delay 9e6 hold; see truth table above for function; this input is connected to output voltage across pullup resistor of 50 k w 13 q 5-v output; block to gnd with 22- m f capacitor, esr < 3 w 6, 14 n.c. not connected p-dso-14-8 aep02710 e6 gnd n.c. n.c. r gnd q 10 9 gnd gnd 1 2 3 4 5 gnd 6 7d 14 13 12 11 e2 gnd 8 i
tle 4267 semiconductor group 6 1999-03-12 block diagram aeb01482 saturation control and protection circuit turn-on/turn-off logic reset generator buffer control amplifier sensor q d r e2 gnd output reset delay reset output input i temperature reference bandgap adjustment 5 v e6 hold inhibit gnd
tle 4267 semiconductor group 7 1999-03-12 absolute maximum ratings t j = C 40 to 150 c parameter symbol limit values unit notes min. max. input voltage v i C 42 42 v C voltage v i C60v t 400 ms current i i C C C limited internally reset output voltage v r C 0.3 7 v C current i r C C C limited internally reset delay voltage v d C 0.3 42 v C current i d CCCC output voltage v q C 0.3 7 v C current i q C C C limited internally inhibit voltage v e2 C 42 42 v C current i e2 C 5 5 ma t 400 ms hold voltage v e6 C 0.3 7 v C current i e6 C C ma limited internally gnd current i gnd C 0.5 C a C temperatures junction temperature t j C 150 cC storage temperature t stg C 50 150 cC
tle 4267 semiconductor group 8 1999-03-12 operating range parameter symbol limit values unit notes min. max. input voltage v i 5.5 40 v see diagram junction temperature t j C 40 150 cC thermal resistance junction ambient r thja C 65 k/w p-to220-7-3 package junction-case r thjc C 6 k/w p-to220-7-3 package junction-case z thjc C 2 k/w t < 1 ms p-to220-7-3 package junction ambient r thja C 70 k/w p-to220-7-180 (smd) package junction-case r thjc C 6 k/w p-to220-7-180 (smd) package junction-case z thjc C 2 k/w t < 1 ms p-to220-7-180 (smd) package junction ambient r thja C 65 k/w p-to220-7-230 package junction-case r thjc C 6 k/w p-to220-7-230 package junction-case z thjc C 2 k/w t < 1 ms p-to220-7-230 package junction ambient r thja C 70 k/w p-dso-14-8 package junction-pin r thjp C 30 k/w p-dso-14-8 package
tle 4267 semiconductor group 9 1999-03-12 characteristics v i = 13.5 v; C 40 c < t j < 125 c; v e2 > 4 v (unless specified otherwise) parameter symbol limit values unit test condition min. typ. max. output voltage v q 4.9 5 5.1 v 5 ma i q 400 ma 6 v v i 26 v output voltage v q 4.9 5 5.1 v 5 ma i q 150 ma 6 v v i 40 v output-current limiting i q 500 C C ma t j = 25 c current consumption i q = i i C i q i q CC50 m a regulator-off current consumption i q = i i C i q i q C 1.0 10 m a t j = 25 c ic turned off current consumption i q = i i C i q i q C 1.3 4 ma i q = 5 ma ic turned on current consumption i q = i i C i q i q CC60ma i q = 400 ma current consumption i q = i i C i q i q CC80ma i q = 400 ma v i = 5 v drop voltage v dr C 0.3 0.6 v i q = 400 ma 1) load regulation d v q CC50mv5 ma i q 400 ma supply-voltage regulation d v q C 1525mv v i = 6 to 36 v; i q = 5 ma supply-voltage rejection svr C54Cdb f r = 100 hz; v r = 0.5 v pp longterm stability d v q C0Cmv 1000 h 1) drop voltage = v i C v q (measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5 v)
tle 4267 semiconductor group 10 1999-03-12 characteristics (contd) parameter symbol limit values unit test condition min. typ. max. reset generator switching threshold v rt 4.2 4.5 4.8 v C reset high level C 4.5 C C v r ext = saturation voltage v r C 0.1 0.4 v r r = 4.7 k w 1) 1) the reset output is low between v q = 1 v and v rt pullup r r C30Ck w C saturation voltage v d,sat C 50 100 mv v q < v rt charge current i d 81525 m a v d = 1.5 v delay switching threshold v dt 2.6 3 3.3 v C delay t d C20Cms c d = 100 nf switching threshold v st C 0.43 C v C delay t t C2C m s c d = 100 nf inhibit turn-on voltage v e2 C34vic turned-on turn-off voltage v e2 2CCvic turned-off pulldown r e2 50 100 200 k w C hysteresis d v e2 0.2 0.5 0.8 v C input current i e2 C 35 100 m a v ip2 = 4 v holding voltage v e6 30 35 40 % referred to v q turn-off voltage v e6 60 70 80 % referred to v q pullup r e6 20 50 100 k w C overvoltage protection turn-off voltage v i,ov 42 44 46 v C turn-on hysteresis d v i,ov 2C6vC
tle 4267 semiconductor group 11 1999-03-12 test circuit application circuit aes01483 22 f i q i r v e6 w 4.7 k d r q e2 i e2 i 1000 f 470 nf i i v e2 d c v c gnd i d i v r q v v i tle 4267 mm inhibit gnd e6 hold aes01484 22 f m gnd r q r i 470 nf e2 e6 from c m 100 nf 5 v output e2; eg from terminal 15 to mc input reset 4267 tle inhibit e6 hold
tle 4267 semiconductor group 12 1999-03-12 time response aet01985 t d t t t t < power reset shutdown thermal voltage drop at input undervoltage at output secondary spike bounce load shutdown on sat v r, st v dt v v d, sat rt v off e2, v on v e2, e v r v v d q v i v
tle 4267 semiconductor group 13 1999-03-12 enable and hold behaviour aet01986 v enable inactive, clamped by int. v pull-down resistor gnd by external hold active, clamped to power-on reset 5) 4) 3) c m v hold inactive, pulled up by enable active v sat r, 2) 1) r 3) t d st v v sat d, dt v v rt d e6 e6 v voltage controller shutdown 10) 9) 8) m was released to no switch on via output-low reset than 4 s v for more possible after e6 e6, rel v > hold inactive, released by pulse width smaller than 7) 6) q t c s m 1 m 9) t 8) e6 v v q, v nom q rel e6, v e6, v hold 2) off v e2, e2, v on v e2 1) v i m 4) 6) <1 s 5) m 7) 10) 10 semiconductor group 14 1999-03-12 tle 4267 output voltage v q versus temperature t j charge current i d versus temperature t j drop voltage v dr versus output current i q delay switching threshold v dt versus temperature t j aed01486 -40 4.70 q t v i = 5.10 v 4.80 4.90 5.00 13.5 v c 0 40 80 160 v j aed01485 -40 i d t v i = 13.5 v c 0 40 80 160 a v c =0 v m 10 12 14 16 18 22 d i j aed01488 0 0 i q c t 125 c =25 = t 100 200 300 400 500 mv 700 100 200 300 400 ma 600 dr v j j aed01487 -40 0 dt t v i = 13.5 v c 0 40 80 160 0.5 1.0 1.5 2.0 2.5 3.0 v 4.0 v dt v j
semiconductor group 15 1999-03-12 tle 4267 current consumption i q versus output current i q output current i q versus temperature t j current consumption i q versus input voltage v i output current i q versus input voltage v i aed01490 0 0 i q 10 20 30 40 50 ma 70 100 200 300 400 ma 600 i q v i = 13.5 v aed01489 -40 i q t c 0 40 80 160 ma 100 200 300 400 500 700 0 13.5 v = i v j aed01491 0 0 q i = 10 20 30 50 r l i v v w 25 5 10 ma 15 0 0 aed01987 i q v v i ma 100 200 300 400 500 600 700 10 20 30 40 50 125 c = = c 25 j t j t
semiconductor group 16 1999-03-12 tle 4267 output voltage v q versus inhibit voltage v e2 inhibit current i e2 versus inhibit voltage v e2 0 0 aed01988 v q 2 4 v 6 1 3 5 e2 v 1 2 3 4 5 6 v 0 0 aed01989 i e2 v v e2 1 2 3 4 5 6 10 20 30 40 50 a m
tle 4267 semiconductor group 17 1999-03-12 package outlines p-to220-7-3 (plastic transistor single outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm
tle 4267 semiconductor group 18 1999-03-12 1.27 0.6 6 x 1.27 = 7.62 0.25 m 10.5 8 9.9 0.1 4.4 2.4 1.5 9.2 0.5 1) 0.15 +0.1 -0.03 ab -0.02 1.3 +0.1 0.2 3.6 0.3 0.4 +0.15 6.6 7.5 6.5 (1.3) b a (14.1) 0.05 0.1 b 0 ... 0.15 5 +3 1) shear and punch direction no burrs this surface all metal surfaces tin plated, except area of cut back side, heatsink contour p-to220-7-180 (plastic transistor single outline) gpt05754 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device
tle 4267 semiconductor group 19 1999-03-12 p-to220-7-230 (plastic transistor single outline) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm
tle 4267 semiconductor group 20 1999-03-12 p-dso-14-8 (plastic dual small outline) gps09222 sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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